A Digital Phase Locked Loop based System for Nakagami -m fading Channel Model
نویسندگان
چکیده
Index Terms Computer Science [1] Fahim, A. M. And Elmasry, M. I. 2003. A Fast Lock Digital Phase-locked-loop Architecture For Wireless Applications, Ieee Transactions On Circuits And Systems-ii: Analog And Digital Signal Processing, Vol. 50, No. 2, Feb. , 2003. [2] Saber, M. , Jitsumatsu,y. And Khan, M. t. a. 2010. Design And Implementation Of Low Power Digital Phase-locked Loop, Proceedings Of The Isita2010, Taichun, Taiwan, Pp. 928 – 933, Oct. , 2010. [3] Stefan, M. And Christian, V. 2008. Improved Lock-time In All-digital Phase-locked Loops Due To Binary Search Acquisition, Proceedings Of The 15th Ieee International Conference On Electronics, Circuits And Systems, Icecs 2008, Malta, Pp. 384-387, 2008. [4] Staszewski, R. B. And Balsara, P. T. 2005. Phase-domain All-digital Phase-locked Loop, Ieee Transactions On Circuits And Systems—ii: Express Briefs, Vol. 52, No. 3, Mar. , 2005. [5] Gill, G. s. And Gupta, S. c. 1972. First-order Discrete
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